1. Field of the Invention
The present invention generally relates to the art of electronic waveform sampling circuits, and more specifically to a sample-and-hold circuit including a push-pull transconductance current amplifier and current mirrors for high slew current, fast signal acquisition and high linearity.
2. Description of the Related Art
Sample-and-hold circuits charge a holding element, which is usually a capacitor, to the instantaneous amplitude of an analog input signal during a tracking or sampling interval, and then disconnect the input signal from the capacitor during a holding interval. The sampled voltage which is held by the capacitor is typically applied to an analog-to-digital converter which produces a corresponding digital value which is stored in a random access memory of a waveform processing unit. A set of stored digital values obtained at increments of a sampled waveform constitutes a digital approximation of the analog signal, and can be analyzed or processed using a variety of known algorithms in accordance with a particular application.
A typical prior art sample-and-hold circuit is described in U.S. Pat. No. 4,659,945, entitled "SAMPLING BRIDGE", issued Apr. 21, 1987 to A Metz. The circuit includes diodes which are connected in a bridge configuration and alternatingly switched between forward and reverse bias to couple an input signal to a capacitor for sampling, and to disconnect the input signal from the capacitor for holding.
The basic diode bridge sample-and-hold circuit does not provide input buffering, and the preceding stage is required to supply the dynamic slew current in the sampling mode. In addition, the sampled pedestal as well as the D.C. offset are determined by the matching of the diode pairs.
The effect of the diode mismatch can be reduced by decreasing the D.C. bias current through the diodes in sampling mode. This, however, reduces the maximum dynamic slew current which is available for charging and discharging the capacitor, thereby limiting the slew rate and increasing the signal acquisition time during the transition from holding to sampling mode.
As another drawback, the maximum dynamic slew current in the basic diode bridge is limited to one-half of the D.C. standing or bias current flowing through the circuit. This also limits the slew rate and increases the acquisition time.
An improved sample-and-hold circuit which uses diodes as switching elements is disclosed in article entitled "A 1.2-.mu.m Bicmos Sample-and-Hold Circuit with a Constant-Impedance Slew-Enhanced Sampling Gate", by M. Wakayama et al, in IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, Dec. 1992, pp. 1697-1708. This circuit is illustrated in FIG. 1 and designated as 10.
The circuit 10 includes diodes D1 to D4 which are connected in an arrangement which resembles, but does not function as a bridge. A voltage input signal VIN is applied to the bases of NPN bipolar transistors Q1 and Q2. The emitters of the transistors Q1 and Q2 are connected to the collectors of similar transistors Q3 and Q4 respectively, the emitters of which are connected to a constant current source IS1 which sinks a constant current IBIAS.
The emitter of the transistor Q1 is also connected to the cathode of the diode D1 and the anode of the diode D3. The emitter of the transistor Q2 is connected to the anode of the diode D2 and the cathode of the diode D4. The junction of the diodes D1 and D2 is connected across a capacitor C1 which produces an output voltage VOUT1. The junction of the diodes D3 and D4 is connected across a capacitor C2 which produces an output voltage VOUT2.
The collectors of the transistors Q1 and Q2 are connected to the input of a current mirror 12 to produce a reference current IREF. The current mirror 12 generates output currents IOUT1 and IOUT2 which are each equal to IREF and are applied to the emitters of the transistors Q1 and Q2 respectively.
The circuit 10 is periodically switched such that the capacitor C1 is charged or discharged to sample the input signal VIN while the capacitor C2 is disconnected to hold the input signal VIN as previously sampled, and vice-versa.
When a TRACK1/HOLD2 switching signal applied to the base of the transistor Q3 is high and a TRACK2/HOLD1 switching signal applied to the base of the transistor Q4 is low, the capacitor C1 operates in sampling mode and the capacitor C2 operates in holding mode. The transistors Q1 and Q3 are turned on and the transistors Q2 and Q4 are turned OFF. The diodes D1 and D2 are forward biased and the diodes D3 and D4 are reverse biased. The capacitor C2 is effectively disconnected from the rest of the circuit 10 and holds the voltage to which it was charged when it was previously operated in sampling mode.
Under static conditions, the mirror currents IREF, IOUT1 and IOUT2 are each equal to IBIAS/3 and flow through the transistor Q1 into the source IS1. The path for the current OUT2 is through the diodes D2 and D1. The signal VIN is coupled to the capacitor C1 through the transistor Q1 and the diode D1. The voltage VIN is reduced by one forward-biased diode drop Vbe across the base-emitter junction of the transistor Q1, and increased by one diode drop Vbe across the diode D1. The voltage VOUT1 is therefore substantially equal to the voltage VIN.
An increase in the input signal VIN causes the voltage at the emitter of the transistor Q1 to temporarily increase above VOUT1, and reverse bias the diode D1. The collector current of the transistor Q1, which constitutes the input current IREF of the current mirror 12, increases, thereby causing the output currents IOUT1 and IOUT2 to increase. The increased output current IOUT2 charges the capacitor C1 until VOUT1 becomes equal to VIN.
When the input signal VIN decreases, the diode D1 becomes forward biased and the capacitor C1 discharges through the diode D1 and the transistor Q3 into the source IS1 until VOUT1 becomes equal to VIN.
When the TRACK1/HOLD2 switching signal applied to the base of the transistor Q3 is low and the TRACK2/HOLD1 switching signal applied to the base of the transistor Q4 is high, the capacitor C1 operates in holding mode and the capacitor C2 operates in sampling mode. The operation is essentially similar to that described above, except that the transistors Q2 and Q4 and diodes D3 and D4 are operative rather than the transistors Q1 and Q3 and diodes D3 and D4.
The circuit 10 improves over the basic diode bridge circuit disclosed in the Metz patent in that the transistors Q1 and Q2 provide input buffering, and the current mirror increases the dynamic slew current by a factor of two. However, the circuit 10 suffers from the same limitation of the basic bridge circuit in that the maximum slew current is limited to the bias current provided by the source IS1.
Assuming that the capacitor C1 is operating in sampling mode and the capacitor C2 is operating in holding mode, the maximum current available for charging or discharging the capacitor C1 is equal to IBIAS. Since the reference current IREF of the current mirror 12 must be supplied by the current source IS1, its maximum value is limited to IBIAS. Since IOUT2 is equal to IREF, the maximum current available for charging the capacitor Cl is also equal to IBIAS.
For a value of VIN which is low enough to turn off the transistor Q1, the capacitor C1 discharges through the diode D1 and transistor Q3 into the source IS1. Since the maximum current the source IS1 can sink is IBIAS, the maximum discharge current is equal to IBIAS.
In summary, the maximum dynamic slew current which is available in the circuit 10 in sampling mode is limited to the standing or bias current IBIAS. This limits the slew rate and signal acquisition rate of the circuit to relatively low values. The circuit 10 also suffers from the drawback of the basic bridge circuit in that, due to the mismatch between the diodes D1 to D4, any attempt to increase the slew rate by increasing the bias current will cause a corresponding detrimental increase in the sampled pedestal and D.C. offset.